This invention relates to organizations for a two-wire 21/2D coincident current core memory comprised of an array of toroidal cores, each core having a bit line driven by half select current and a word select line driven by half select current, and more particularly to organization for bit select (Y drive) lines time shared to read for both drive and sense functions with cancellation of cross-coupled noise from word select (X drive) lines.
In a two-line 21/2D memory, selected X and Y drive lines are energized with half select current of the proper polarity for both read and write operations. Typically, the X line selects a word consisting of a number of bits, but first a number of Y drive lines are energized to select the bits. Thus, to read a word, the selected bit lines are energized, and after all ringing of the bit lines has subsided, the word line is energized. Both X and Y drive currents for each bit will have the same direction through the core to set it to the bit 0 state. If the core had previously stored a bit 1, the flux of the core being switched to a bit 0 reduces a pulse on its bit line. The bit line may thus be used as a sense line, provided noise from the word select pulse also induced into the bit line can be cancelled. There are three configurations commonly used for achieving that cancellation.
One configuration, shown in FIG. 1a, uses the same Y bit drive current to energize two bit lines L1 and L2 equally. One bit line passes through its cores in one direction relative to the X word drive line W1, and the other bit lines passes through its cores in the other direction. Since the word drive line passes through corresponding cores of both bit lines in the same direction, only one core is "selected" to receive coincident half select current for read, or write, of the same sense, i.e., direction through the core. The other core receives half select current in one direction, and the other half in the other direction, so it is not switched. The paired lines are connected to a differential sense amplifier 10 so that only the difference in the currents on the paired sense lines will be amplified. As a consequence, the effects of the X drive pulse in the two lines will cancel, and only the line with the selected core that is switched will have any uncancelled current pulse which is sensed and amplified as a bit 1. A memory system employing this configuration for common-mode signal rejection is disclosed by the inventor in U.S. Pat. No. 3,693,176.
A second configuration very similar to the first employs paired bit drive lines, but instead of placing the corresponding cores of two different words on the two different bit lines L1 and L2, they are placed on the same bit lines, and the word select line W1 is folded as shown in FIG. 1b so that the word select pulse cancels itself on the selected bit line. Another variation folds the bit lines instead, as shown in FIG. 1c. These folded-line arrangements have a significant packaging advantage (lower wire termination density) over the unfolded arrangement of balanced sense lines and word lines in FIG. 1a, which allows significant cost reduction.
In any of these arrangements, the sense amplifier 10 is preferably coupled to the bit drive lines by a balun transformer T1 shown in FIG. 2 for the arrangement of FIG. 1c. However, magnetic and capacitive coupling between word and bit lines with either of the folded or the unfolded arrangements is now inherently imbalanced, and such imbalance can be minimized only by elaborate packaging methods. What is required is an arrangement which does not require balanced magnetic and capacitive coupling, yet still permits selecting paired bit lines for reading out a word, one bit out of each pair of bit lines with cancelled X word drive current induced into the Y bit drive lines.